The present application relates generally to semiconductor devices, and more specifically to vertically-stacked nanosheet or nanowire transistors and their methods of production.
A nanosheet or a nanowire field effect transistor (FET) includes plural layers of nano-dimensional semiconductor material that function as the channel regions of the device. Such nanosheet- or nanowire-based structures enable feature scaling beyond current two-dimensional CMOS technology. However, conventional fabrication methods that use alternating sacrificial layers to offset the active nanostructures with respect to one another as well as template their growth may yield undesirable variation in the length of the channel region amongst the various active layers. Such variation can result from geometric effects associated with patterning and etching a stack of layers.
Shown in FIG. 1, for example, is an TEM micrograph of a comparative nanowire transistor at an intermediate stage of fabrication. The device includes a semiconductor substrate 10 with an array of alternately stacked layers 20, 30 formed thereon. The array of layers includes sacrificial silicon germanium (SiGe) layers 20 and active silicon (Si) layers 30. During subsequent fabrication, the sacrificial layers 20 of silicon germanium are removed and replaced with a gate all around (GAA) architecture that includes gate dielectric and gate conductor layers (not shown). However, as will be appreciated, the length (LG1, LG2, LG3) of the sacrificial silicon germanium layers 20 is not uniform throughout the device, which results in non-uniformity in the effective gate length after formation of the gate layers. Such gate length non-uniformity may adversely affect the performance and reliability of the device.